CRC encoding circuit, CRC encoding method, data sending device and data receiving device

ABSTRACT

A CRC encoding circuit for generating a CRC code in accordance with initial parallel data having remainder portion data in a last column of the initial parallel data, comprises: a first parallel encoding unit for generating a first CRC code in accordance with the initial parallel data other than the remainder portion data; a CRC code selector for selecting a second CRC code having predetermined number of bytes, from the first CRC code generated by the first parallel encoding unit; a parallel data selector for selecting second parallel data having the same number of bytes as the second CRC code, from the remainder portion data; and a second parallel encoding unit for generating a third CRC code in accordance with the second CRC code and the second parallel data.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a CRC encoding circuit forgenerating a CRC code from parallel data which is inputted asvariable-length data, and to a CRC encoding method therefor. Further,the present invention relates to a data sending device and a datareceiving device for detecting an error of data in the datacommunication by using the CRC encoding circuit.

[0003] 2. Description of Earlier Development

[0004] According to an earlier development, a CRC (Cyclic RedundancyCheck) which has high ability to detect an error in a digitalcommunication, is used. The CRC means an error detection method fordetecting an error of data by making a comparison between the CRC codegenerated in a sender and the CRC code generated in a receiver.

[0005] Recently, for example, like POS (PPP Over SONET/SDH), thehigh-speed variable-length data communication which performscommunication from end to end by framing a low-speed variable-lengthdata frame (PPP frame) over a high-speed variable-length data frame(SONET/SDH frame), is utilized widely. A CRC encoding circuit whichgenerates a CRC code in accordance with the inputted n-byte(s) paralleldata, has been introduced as means for detecting an error of data insuch high-speed variable-length data communication.

[0006] Hereinafter, a former CRC encoder will be explained withreference to the drawings. FIG. 3 shows circuit composition of a CRCencoding circuit 21. As shown in FIG. 3, a CRC encoding circuit 21mainly comprises a 16-bytes parallel CRC encoder 22, each n-byte(s)parallel CRC encoder 23 to 37 (n=1 to 15), and a selector (SEL) 38.

[0007] In the 16-bytes parallel data outputted from an external circuit,the parallel data other than the remainder portion data of the lastcolumn is encoded by the 16-bytes parallel CRC encoder 22. As a result,a CRC code is outputted as an encoded interim result. On the other hand,the remainder portion data of the last column is encoded by any one ofthe n-byte(s) parallel CRC encoders corresponding to the number of thebyte(s) of the inputted remainder portion data, in accordance with theencoded interim result, and then is outputted to the SEL 38. The SEL 38selects the desired CRC code from the inputted plurality of CRC codes,and outputs the desired CRC code as a final encoded result.

[0008]FIG. 4 is the view showing circuit composition of a former CRCencoding circuit 41. As shown in FIG. 4, the CRC encoding circuit 41comprises a 16-bytes parallel CRC encoder 42, a byte serializer 43, a1-byte serial CRC encoder 44, and a selector (SEL) 45.

[0009] In the 16-bytes parallel data outputted from an external circuit,the parallel data other than the remainder portion data of the lastcolumn is encoded by the 16-bytes parallel CRC encoder 42. As a result,a CRC code is outputted as an encoded interim result. On the other hand,the remainder portion data of the last column is converted to bytesserial data by the byte serializer 43. The converted data is encoded bythe 1-byte serial CRC encoder 44 in accordance with the CRC code, and isoutputted to the SEL 45. Then, the SEL 45 selects the desired CRC codefrom the inputted plurality of CRC codes, and outputs the desired CRCcode as a final encoded result.

[0010] Although the above-mentioned CRC encoding circuits 21 and 41 wereuseful as a remedy for processing less than 16 bytes of data, there werethe following problems. Firstly, in the case that, for example,variable-length data is 16-bytes data, a total of 16 n-byte(s) parallelCRC encoders including the CRC encoder(s) which is not actually used,are required in the CRC encoding circuit 21. Thus, a total of 2^(n)−1byte(s) parallel CRC encoders are required as the number of bytes of theinputted 2^(n)-byte(s) parallel data increases. Therefore, themanufacturing costs of the CRC encoding circuit increases with thecircuit scale of the CRC encoding circuit.

[0011] Further, in the case of the CRC encoding circuit 41, although thegeneration of a CRC code can be realized with one byte parallel CRCencoder, the 1-byte serial CRC encoder is to be used 2^(n)−1 times atthe maximum when byte(s) parallel data is converted to byte(s) serialdata. Thus, in the case that the n of the inputted 2^(n)-bytes paralleldata is 2 or more, variable-length data cannot be processed insequential order.

SUMMARY OF THE INVENTION

[0012] An object of the present invention is to provide a CRC encodingcircuit and a CRC encoding method which can suppress the number of theCRC encoders to be used and generate a CRC code in accordance with2^(n)-bytes parallel data inputted in sequential order asvariable-length data.

[0013] In order to solve the above problems, in accordance with a firstaspect of the invention, a CRC encoding circuit for generating a CRCcode in accordance with an initial parallel data having a remainderportion data in a last column of the initial parallel data, comprises:

[0014] a first parallel encoding unit for generating a first CRC code inaccordance with the initial parallel data other than the remainderportion data;

[0015] a CRC code selector for selecting a second CRC code havingpredetermined number of bytes, from the first CRC code generated by thefirst parallel encoding unit;

[0016] a parallel data selector for selecting a second parallel datahaving the same number of bytes as the second CRC code, from theremainder portion data; and

[0017] a second parallel encoding unit for generating a third CRC codein accordance with the second CRC code and the second parallel data. Theinitial parallel data may be 2^(n)-bytes parallel data, and thepredetermined number may be 2^(n−m), where n is a natural number and mis a natural number selected from 1 to n.

[0018] The CRC encoding circuit may further comprise:

[0019] a detecting unit for detecting the remainder portion data fromthe last column of the initial parallel data; and

[0020] wherein the parallel data selector selects the second paralleldata having the predetermined number of bytes, from the reminder portiondata detected by the detecting unit.

[0021] The initial parallel data may be a variable-length data.

[0022] In accordance with a second aspect of the invention, a CRCencoding method for generating a CRC code in accordance with an initialparallel data having a remainder portion data in a last column of theinitial parallel data, comprises the steps of:

[0023] generating a first CRC code in accordance with the initialparallel data other than the remainder portion data;

[0024] selecting a second CRC code having predetermined number of bytes,from the generated first CRC code;

[0025] selecting a second parallel data having the same number of bytesas the second CRC code, from the remainder portion data; and

[0026] generating a third CRC code in accordance with the second CRCcode and the second parallel data.

[0027] The initial parallel data may be a 2^(n)-bytes parallel data, andthe predetermined number may be 2^(n−m), where n is a natural number andm is a natural number selected from 1 to n.

[0028] The CRC encoding method may further comprise the steps of:

[0029] detecting the remainder portion data from the last column of theinitial parallel data;

[0030] wherein the second parallel data having the predetermined numberof bytes is selected from the detected reminder portion data.

[0031] The initial parallel data may be a variable-length data.

[0032] In accordance with a third aspect of the invention, a datasending device comprises:

[0033] a CRC encoding circuit for generating a CRC code in accordancewith an initial parallel data having a remainder portion data in a lastcolumn of the initial parallel data, comprises: a first parallelencoding unit for generating a first CRC code in accordance with theinitial parallel data other than the remainder portion data; a CRC codeselector for selecting a second CRC code having predetermined number ofbytes, from the first CRC code generated by the first parallel encodingunit; a parallel data selector for selecting a second parallel datahaving the same number of bytes as the second CRC code, from theremainder portion data; and a second parallel encoding unit forgenerating a third CRC code in accordance with the second CRC code andthe second parallel data.

[0034] The initial parallel data may be a 2^(n)-bytes parallel data, andthe predetermined number may be 2^(n−m), where n is a natural number andm is a natural number selected from 1 to n.

[0035] The CRC encoding circuit may further comprise:

[0036] a detecting unit for detecting the remainder portion data fromthe last column of the initial parallel data;

[0037] wherein the parallel data selector selects the second paralleldata having the predetermined number of bytes, from the reminder portiondata detected by the detecting unit.

[0038] The initial parallel data may be a variable-length data.

[0039] In accordance with a fourth aspect of the invention, a datareceiving device comprises:

[0040] a CRC encoding circuit for generating a CRC code in accordancewith an initial parallel data having a remainder portion data in a lastcolumn of the initial parallel data, comprises: a first parallelencoding unit for generating a first CRC code in accordance with theinitial parallel data other than the remainder portion data; a CRC codeselector for selecting a second CRC code having predetermined number ofbytes, from the first CRC code generated by the first parallel encodingunit; a parallel data selector for selecting a second parallel datahaving the same number of bytes as the second CRC code, from theremainder portion data; and a second parallel encoding unit forgenerating a third CRC code in accordance with the second CRC code andthe second parallel data.

[0041] The initial parallel data may be a 2^(n)-bytes parallel data, andthe predetermined number may be 2^(n−m), where n is a natural number andm is a natural number selected from 1 to n.

[0042] The CRC encoding circuit may further comprise:

[0043] a detecting unit for detecting the remainder portion data fromthe last column of the initial parallel data;

[0044] wherein the parallel data selector selects the second paralleldata having the predetermined number of bytes, from the reminder portiondata detected by the detecting unit.

[0045] The initial parallel data may be a variable-length data.

[0046] According to the present invention, even when the parallel datawith a long frame, such as 16-bytes parallel data, is sequentiallyinputted into the CRC encoding circuit, the CRC code of the inputtedparallel data can be generated by using simple circuit composition. Thiscan suppress an increase in circuit scale and in manufacturing cost.

BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The present invention will become more fully understood from thedetailed description given hereinbelow and the accompanying drawingwhich are given by way of illustration only, and thus are not intendedas a definition of the limits of the present invention, and wherein;

[0048]FIG. 1 shows circuit composition of a CRC encoding circuit 1according to the present invention;

[0049]FIG. 2 shows a view for explaining the procedure which generates aCRC code in accordance with 16-bytes parallel data by using the CRCencoding circuit of FIG. 1;

[0050]FIG. 3 shows circuit composition of a former CRC encoding circuit21; and

[0051]FIG. 4 shows circuit composition of a former CRC encoding circuit41.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0052] Hereinafter, a CRC encoding circuit and a CRC encoding method inaccordance with the present invention, will be explained with referenceto the drawings.

[0053] In the present embodiment, for explanation ease, the generationof a CRC code from 16-bytes parallel data will be explained.

[0054] Firstly, the composition of the embodiment will be explained.

[0055] As shown in FIG. 1, a CRC encoding circuit 1 mainly comprises a16-bytes parallel CRC encoder 2 (hereinafter, simply referred to as “a16-bytes encoder 2”), an 8-bytes parallel CRC encoder 3 (hereinafter,simply referred to as “an 8-bytes encoder 3”), a 4-bytes parallel CRCencoder 4 (hereinafter, simply referred to as “a 4-bytes encoder 4”), a2-bytes parallel CRC encoder 5 (hereinafter, simply referred to as “a2-bytes encoder 5”), a 1-byte parallel CRC encoder 6 (hereinafter,simply referred to as “a 1-byte encoder 6”), a 15-bytes parallel dataselecting section 7 (hereinafter, simply referred to as “a 15-bytesselecting section 7”), a 7-bytes parallel data selecting section 8(hereinafter, simply referred to as “a 7-bytes selecting section 8”), a3-bytes parallel data selecting section 9 (hereinafter, simply referredto as “a 3-bytes selecting section 9”), a control unit 10 and aplurality of latches 11.

[0056] The 16-bytes encoder 2 comprises a 16-bytes parallel encodingunit 2 a, a CRC code selector (SEL) 2 b and a CRC code selector (SEL) 2c. In the case that the variable-length 16-bytes parallel data outputtedfrom an external circuit (not shown) is 16 bytes or more, the 16-bytesencoder 2 encodes the data (shown in FIG. 2 D1, D2) other than the lastcolumn to a CRC code by 16 bytes in accordance with an initial value100, by synchronizing with control signals outputted from the controlunit 10. Then, the result of the encoding is outputted to the 8-bytesencoder 3. In this case, the SEL 2 c of the 16-bytes encoder 2 selectsthe CRC code generated by the 16-bytes parallel encoding unit 2 a. Onthe other hand, in the case that the inputted 16-bytes parallel data isless than 16 bytes, the 16-bytes encoder 2 outputs the initial value 100to the 8-bytes encoder 3 without encoding the less than 16 bytes data toa CRC code.

[0057] The 8-bytes encoder 3 comprises a 8-bytes parallel encoding unit3 a, a CRC code selector (SEL) 3 b and a latch 3 c. The 8-bytes encoder3 selects either the data generated by encoding the data outputted fromthe 15-bytes selecting section 7 by using the 8-bytes parallel encodingunit 3 a, or the data generated by latching the encoded interim resultfrom the 16-bytes encoder 2 in the latch 3 c, by synchronizing with acontrol signal outputted from the control unit 10. Then, the selecteddata is outputted to the 4-bytes encoder 4.

[0058] Concretely, on one hand, in the case that the remainder portiondata of the last column (see FIG. 2) is 8 to 15 bytes, the 8-bytesencoder 3 encodes the 8-bytes parallel data outputted from the 15-bytesselecting section 7 to a CRC code, in accordance with the data outputtedfrom the 16-bytes encoder 2 as an initial value for encoding the data.Then, the result of the encoding is outputted to 4-bytes encoder 4. Inthis case, the SEL 3 b of the 8-bytes encoder 3 selects the CRC codegenerated by the 8-bytes parallel encoding unit 3 a. On the other hand,in the case that the remainder portion data of the last column (see FIG.2) is less than 8 bytes, the 8-bytes encoder 3 latches the dataoutputted from the 16-bytes encoder 2 without encoding the less than 8bytes of the data to a CRC code. Then, the latched data is outputted tothe 4-bytes encoder 4. In this case, the SEL 3 b selects the datagenerated by latching the encoded interim result from the 16-bytesencoder 2.

[0059] Similarly, the 4-bytes encoder 3 comprises a 4-bytes parallelencoding unit 4 a, a CRC code selector (SEL) 4 b and a latch 4 c. The4-bytes encoder 4 selects either the data generated by encoding the dataoutputted from the 7-bytes selecting section 8 by using the 4-bytesparallel encoding unit 4 a, or the data generated by latching theencoded interim result from the 8-bytes encoder 3 in the latch 4 c, bysynchronizing with a control signal outputted from the control unit 10.Then, the selected data is outputted to the 2-bytes encoder 5.

[0060] Concretely, on one hand, in the case that the unencoded remainderportion data of the last column is 4 to 7 bytes, the 4-bytes encoder 4encodes the 4-bytes parallel data outputted from the 7-bytes selectingsection 8 to a CRC code, in accordance with the data outputted from the8-bytes encoder 3 as an initial value for encoding the data. Then, theresult of the encoding is outputted to 2-bytes encoder 5. In this case,the SEL 4 b of the 4-bytes encoder 4 selects the CRC code generated bythe 4-bytes parallel encoding unit 4 a. On the other hand, in the casethat the unencoded remainder portion data in the last column data isless than 4 bytes, the 4-bytes encoder 4 latches the data outputted fromthe 8-bytes encoder 3 without encoding the less than 4 bytes of the datato a CRC code. Then, the latched data is outputted to the 2-bytesencoder 5. In this case, the SEL 4 b selects the data generated bylatching the encoded interim result from the 8-bytes encoder 3.

[0061] Further similarly, the 2-bytes encoder 5 selects either the datagenerated by encoding the data outputted from the 3-bytes selectingsection 9 by using a 2-bytes parallel encoding unit 5 a, or the datagenerated by latching the encoded interim result from the 4-bytesencoder 4 in a latch 5 c. Then, the selected data is outputted to the1-byte encoder 6. Further, the 1-byte encoder 6 selects either the datagenerated by encoding the data outputted from the 3-bytes selectingsection 9 by using a 1-bytes parallel encoding unit 6 a, or the datagenerated by latching the encoded interim result from the 2-bytesencoder 5 in a latch 6 c. Then, the selected data is outputted as afinal encoded result.

[0062] The 15-bytes selecting section 7 comprises a parallel dataselector (SEL) 7 a and a latch 7 b. In the case that the last columndata of the 16-bytes parallel data, which is outputted from an externalcircuit (not shown), is 8 to 15 bytes (shown in FIG. 2, D3), the15-bytes selecting section 7 outputs upper 8-bytes data of the lastcolumn data to the 8-bytes encoder 3, and latches remaining lower datain the latch 7 b to output the latched data to the 7-bytes selectingsection 8, by synchronizing with the control signal outputted from thecontrol unit 10. On the other hand, in the case that the last columndata is less than 8 bytes, the 15-bytes selecting section 7 does notoutput the less than 8 bytes of the data to the 8-bytes encoder 3 butlatches the less than 8 bytes of the data in the latch 7 b. Then, the15-bytes selecting section 7 outputs the latched less than 8 bytes ofthe data to the 7-bytes selecting section 8.

[0063] Similarly, in the case that the remaining data (unencoded data)of the last column, which is outputted from the latch 7 b, is 4 to 7bytes, the 7-bytes selecting section 8 outputs upper 4-bytes data of theremaining data to the 4-bytes encoder 4, and latches the remaining lowerdata in a latch 8 b to output the latched data to the 3-bytes selectingsection 9. On the other hand, in the case that the remaining data(unencoded data) of the last column, which is outputted from the latch 7b, is less than 4 bytes, the 7-bytes selecting section 8 does not outputthe less than 4 bytes of the data to the 4-bytes encoder 4 but latchesthe less than 4 bytes of the data in the latch 8 b. Then, the 7-bytesselecting section 8 outputs the less than 4 bytes of the data to the3-bytes selecting section 9.

[0064] In the case that the remaining data (unencoded data) of the lastcolumn, which is outputted from the latch 8 b, is 2 to 3 bytes, the3-bytes selecting section 9 outputs upper 2-bytes data of the remainingdata to the 2-bytes encoder 5, and latches the remaining lower data in alatch 9 b to output the latched data to the 1-byte encoder 6. On theother hand, in the case that the remaining data (unencoded data) of thelast column, which is outputted from the latch 8 b, is 1 byte, the3-bytes selecting section 9 do not outputs the 1-byte data to the2-bytes encoder 5 but latches the 1-byte data in the latch 9 b. Then,the 3-bytes selecting section 9 outputs the latched 1-byte data to the1-byte encoder 6.

[0065] The control unit 10 detects the data of the last column of theinputted 16-bytes parallel data (REMAINDER PORTION DATA shown in FIG.2), and the number of the bytes thereof. The control unit 10 outputsvarious control signals which will be mentioned and performs the controlfor generating a CRC code in accordance with the 16-bytes parallel datainputted into the CRC encoding circuit 1.

[0066] The latch 11 latches the various control signals outputted fromthe control unit 10, and outputs the latched signals to a next latch 11and to each of the above-mentioned CRC encoders.

[0067] Here, the 16-bytes parallel data for generating a CRC code andthe various control signals (CRCEN, STROBE, STATE[n] shown in FIG. 1)outputted from the control unit 10 will be explained.

[0068] The 16-bytes parallel data is the communication data with avariable-length data frame, and is inputted into the 16-bytes encoder 2and into the 15-bytes selecting section 7.

[0069] The CRCEN (CRC ENABLE) signal is one which indicates the extentthat a CRC code is generated. The CRCEN signal is inputted into the16-bytes encoder 2 only.

[0070] The STROBE signal is one for indicating the data of the lastcolumn of the 16-bytes parallel data. The STROBE signal is inputted intothe 16-bytes encoder 2, the 8-bytes encoder 3, and the latch 11respectively.

[0071] The STATE[n] signal is one for indicating the number of the bytesincluded in the data of the last column which is indicated by theabove-mentioned STROBE signal. The STATE[n] signal is inputted into the16-bytes encoder 2, the SEL 7 a, and the latch 11 respectively.

[0072] Next, the operation of the CRC encoding circuit 1 in accordancewith the present invention, will be explained. The procedure forgenerating a CRC code in accordance with 16-bytes parallel data will beexplained with reference to FIG. 1 and FIG. 2.

[0073] As shown in FIG. 2, the 16-bytes parallel data “D” with 47-bytesframe lengths (1 to 47) has three columns D1 (1 to 16), D2 (17 to 32),D3 (33 to 47) of parallel data. The last column D3 has 15 bytes ofremainder portion data (33 to 47) and 1 byte of ineffective data (themesh box shown in FIG. 2).

[0074] On the one hand, the data D1 and D2 of the above-mentioned16-bytes parallel data “D” (the data other than the remainder portiondata D3), is inputted into the 16-bytes encoder 2. The 16-bytes parallelencoding unit 2 a encodes the inputted 16-bytes parallel data D1, D2.The result of the encoding is selected by the SEL 2 c, and the selectedresult is outputted to the 8-bytes encoder 3 as an encoded interimresult “A”. Concretely, at first, the data D1 is encoded by the 16-bytesparallel encoding unit 2 a, thereby a CRC code is generated. Then, thedata D2 is encoded by the 16-bytes parallel encoding unit 2 a inaccordance with the generated CRC code. As a result, a new CRC code isgenerated, and the new CRC code is outputted to the SEL 2 c. The SEL 2 cselects the new CRC code generated by the 16-bytes parallel encodingunit 2 a. Finally, the selected CRC code is outputted to the 8-bytesencoder 3 as the encoded interim result “A”.

[0075] On the other hand, the data D3 of the 16-bytes parallel data “D”,is divided into upper 8-bytes data (33 to 40) and lower 7-bytes data (41to 47) by the 15-bytes selecting section 7. The upper 8-bytes data isinputted into the 8-bytes encoder 3. The lower 7-bytes data is inputtedinto the 7-bytes selecting section 8. In the case that the frame-lengthof the inputted 16-bytes parallel data “D” is less than 16 bytes, theinitial value 100 is inputted into the 8-bytes encoder 3.

[0076] Subsequently, the upper 8-bytes data (33 to 40) outputted fromthe 15-bytes selecting section 7, is encoded to a CRC code by the8-bytes encoder 3 in accordance with the encoded interim result “A”selected by the SEL 2 c as an initial value. Then, the encoded data isinputted into the 4-bytes encoder 4 as an encoded interim result “B”.That is, the SEL 3 b selects the CRC code generated by the 8-bytesparallel encoding unit 3 a. Then, the selected CRC code is inputted intothe 4-bytes encoder 4 as the encoded interim result “B”.

[0077] The lower 7-bytes data (41 to 47) outputted from the 15-bytesselecting section 7, is divided into upper 4-bytes data (41 to 44) andlower 3-bytes data (45 to 47) by the 7-bytes selecting section 8. Theupper 4-bytes data is inputted into the 4-bytes encoder 4. The lower3-bytes data is inputted into the 3-bytes selecting section 9.

[0078] Subsequently, the upper 4-bytes data (41 to 44) outputted fromthe 7-bytes selecting section 8, is encoded to a CRC code by the 4-bytesencoder 4 in accordance with the encoded interim result “B” selected bythe SEL 3 b as an initial value. Then, the encoded data is inputted intothe 2-bytes encoder 5 as an encoded interim result “C”. That is, the SEL4 b selects the CRC code generated by the 4-bytes parallel encoding unit4 a. Then, the selected CRC code is inputted into the 2-bytes encoder 5as the encoded interim result “C”.

[0079] The lower 3-bytes data (45 to 47) outputted from the 7-bytesselecting section 8, is divided into upper 2-bytes data (45 and 46) andlower 1-byte data (47) by the 3-bytes selecting section 9. The upper2-bytes data is inputted into the 2-bytes encoder 5. The lower 1-bytedata is inputted into the 1-byte encoder 6.

[0080] Subsequently, the upper 2-bytes data (45 and 46) outputted fromthe 3-bytes selecting section 9, is encoded to a CRC code by the 2-bytesencoder 5 in accordance with the encoded interim result “C” selected bythe SEL 4 b as an initial value. Then, the encoded data is inputted intothe 1-byte encoder 6 as an encoded interim result “D”. That is, the SEL5 b selects the CRC code generated by the 2-bytes parallel encoding unit5 a. Then, the selected CRC code is inputted into the 1-byte encoder 6as the encoded interim result “D”.

[0081] The lower 1-bytes data (47) outputted from the 3-bytes selectingsection 9, is encoded to a CRC code by the 1-byte encoder 6 inaccordance with the encoded interim result “D” selected by the SEL 5 bas an initial value. Then, the encoded data is outputted as a finalencoded result. That is, the SEL 6 b selects the CRC code generated bythe 1-byte parallel encoding unit 6 a. Then, the selected CRC code isoutputted as the final encoded result.

[0082] As mentioned above, because the CRC encoding circuit 1 inaccordance with the present invention comprises n−1 CRC encoders forencoding 2^(n−m) (m=1 to n)-bytes parallel data, the CRC encodingcircuit 1 has the function that the remainder portion data in a lastcolumn of the 16-bytes parallel data which is inputted asvariable-length data can be encoded and sequentially processed inaccordance with the CRC codes encoded by a plurality of CRC encoders.

[0083] Thus, even when the parallel data having a long frame, such as16-bytes parallel data, is inputted into the CRC encoding circuit 1, theCRC code of the inputted parallel data can be generated by using simplecircuit composition. This can suppress the increase in circuit scale ofthe CRC encoding circuit and in manufacturing cost thereof.

[0084] Furthermore, at most, n byte(s) parallel CRC encoders aresufficient for 2^(n)-bytes parallel data in the CRC encoding circuit ofthe present invention. Thus, even when 4 bytes or more of parallel datais sequentially inputted into the CRC encoding circuit 1, the CRC codeof the parallel data can be generated.

[0085] The content of the description of this embodiment is a suitableexample of the CRC encoding circuit in accordance with the presentinvention. The present invention is not limited to this.

[0086] For example, although the inputted variable-length data is16-bytes parallel data in this embodiment, the present invention may beapplied to 2^(n)-bytes parallel data by having n byte(s) parallel CRCencoders and n−1 bytes parallel data selecting sections. Further, thenumber of bytes of the remainder portion data in a last column ofparallel data, may be optional.

[0087] Furthermore, the CRC encoding circuit in accordance with thepresent invention, may be applied to a data sending device and a datareceiving device. In this case, both of these devices generate a CRCcode. Then, by making a comparison with each of the CRC codes, an errorof data can be detected in the data communication.

[0088] In addition, with respect to the detailed composition of the CRCencoding circuit 1, the detailed operation of the CRC encoding circuit1, or the like, various other changes may be suitably made withoutdeparting from the gist of the present invention.

[0089] The entire disclosure of Japanese Patent Application No. Tokugan2000-333090 filed on Oct. 31, 2000 including specification, claims,drawings and summary are incorporated herein by reference in itsentirety.

What is claimed is:
 1. A CRC encoding circuit for generating a CRC codein accordance with an initial parallel data having a remainder portiondata in a last column of the initial parallel data, comprising: a firstparallel encoding unit for generating a first CRC code in accordancewith the initial parallel data other than the remainder portion data; aCRC code selector for selecting a second CRC code having predeterminednumber of bytes, from the first CRC code generated by the first parallelencoding unit; a parallel data selector for selecting a second paralleldata having the same number of bytes as the second CRC code, from theremainder portion data; and a second parallel encoding unit forgenerating a third CRC code in accordance with the second CRC code andthe second parallel data.
 2. The CRC encoding circuit as claimed inclaim 1, wherein the initial parallel data is a 2^(n)-bytes paralleldata, and the predetermined number is 2^(n−m), where n is a naturalnumber and m is a natural number selected from 1 to n.
 3. The CRCencoding circuit as claimed in claim 1, further comprising: a detectingunit for detecting the remainder portion data from the last column ofthe initial parallel data; and wherein the parallel data selectorselects the second parallel data having the predetermined number ofbytes, from the reminder portion data detected by the detecting unit. 4.The CRC encoding circuit as claimed in claim 1, the initial paralleldata is a variable-length data.
 5. A CRC encoding method for generatinga CRC code in accordance with an initial parallel data having aremainder portion data in a last column of the initial parallel data,comprising the steps of: generating a first CRC code in accordance withthe initial parallel data other than the remainder portion data;selecting a second CRC code having predetermined number of bytes, fromthe generated first CRC code; selecting a second parallel data havingthe same number of bytes as the second CRC code, from the remainderportion data; and generating a third CRC code in accordance with thesecond CRC code and the second parallel data.
 6. The CRC encoding methodas claimed in claim 5, wherein the initial parallel data is a2^(n)-bytes parallel data, and the predetermined number is 2^(n−m),where n is a natural number and m is a natural number selected from 1 ton.
 7. The CRC encoding method as claimed in claim 5, further comprisingthe steps of: detecting the remainder portion data from the last columnof the initial parallel data; wherein the second parallel data havingthe predetermined number of bytes is selected from the detected reminderportion data.
 8. The CRC encoding method as claimed in claim 5, theinitial parallel data is a variable-length data.
 9. A data sendingdevice, comprising: a CRC encoding circuit for generating a CRC code inaccordance with an initial parallel data having a remainder portion datain a last column of the initial parallel data, comprising: a firstparallel encoding unit for generating a first CRC code in accordancewith the initial parallel data other than the remainder portion data; aCRC code selector for selecting a second CRC code having predeterminednumber of bytes, from the first CRC code generated by the first parallelencoding unit; a parallel data selector for selecting a second paralleldata having the same number of bytes as the second CRC code, from theremainder portion data; and a second parallel encoding unit forgenerating a third CRC code in accordance with the second CRC code andthe second parallel data.
 10. The data sending device as claimed inclaim 9, wherein the initial parallel data is a 2^(n)-bytes paralleldata, and the predetermined number is 2^(n−m), where n is a naturalnumber and m is a natural number selected from 1 to n.
 11. The datasending device as claimed in claim 9, wherein the CRC encoding circuitfurther comprises: a detecting unit for detecting the remainder portiondata from the last column of the initial parallel data; wherein theparallel data selector selects the second parallel data having thepredetermined number of bytes, from the reminder portion data detectedby the detecting unit.
 12. The data sending device as claimed in claim9, the initial parallel data is a variable-length data.
 13. A datareceiving device, comprising: a CRC encoding circuit for generating aCRC code in accordance with an initial parallel data having a remainderportion data in a last column of the initial parallel data, comprising:a first parallel encoding unit for generating a first CRC code inaccordance with the initial parallel data other than the remainderportion data; a CRC code selector for selecting a second CRC code havingpredetermined number of bytes, from the first CRC code generated by thefirst parallel encoding unit; a parallel data selector for selecting asecond parallel data having the same number of bytes as the second CRCcode, from the remainder portion data; and a second parallel encodingunit for generating a third CRC code in accordance with the second CRCcode and the second parallel data.
 14. The data receiving device asclaimed in claim 13, wherein the initial parallel data is a 2^(n)-bytesparallel data, and the predetermined number is 2^(n−m), where n is anatural number and m is a natural number selected from 1 to n.
 15. Thedata receiving device as claimed in claim 13, wherein the CRC encodingcircuit further comprises: a detecting unit for detecting the remainderportion data from the last column of the initial parallel data; whereinthe parallel data selector selects the second parallel data having thepredetermined number of bytes, from the reminder portion data detectedby the detecting unit.
 16. The data receiving device as claimed in claim13, the initial parallel data is a variable-length data.